MOVE.L #1000,A0 ;bring address in A0
MOVE #1,(A0) ;write 1 into this address
RECORD:
DC.W 2 ;number of entries -1
DC.W 1,2,3 ;elements of list
CLR.L D0 ;erase D0 completely
MOVE.L #RECORD,A0 ;address of list in A0
MOVE (A0),D0 ;number of elements -1 in D0
MOVE 1(A0,D0),D1 ;last element in D1 ...
RECORD: DC.W 2 ;number of entries -1
DC.W 1,2,3 ;elements of list
CMP #2,D1
CMP #2,D1 ;comparison,or subtraction
BNE UNEQUAL ;branch,if not equal(Z flag not set)
MOVE #0,D2 ;otherwise execute D2=0
UNEQUAL:
T true,corresponds to BRA
F false,never branches
HI higher than C'* Z'
LS lower or same C Z
CC,HS carry clear,higher or same C'
CS,LO carry set,lower C
NE not equal Z'
EQ equal Z
VC overflow clear V'
VS overflow set V
PL plus,positive
MI minus,negative
GE greater or equal N*V N'*V'
LT less than N*V' N'*V
GT greater than N*V*Z' N'*V'*Z'
LE less or equal Z N*V' N'*V
---------------------------------------------------
Bcc Label conditional branch,depends on condition
BRA Label unconditional branch(similar to JMP)
BSR Label branch to subprogram.Return address is
deposited on stack,RTS causes return to that
address.
CHK <ea>,Dx check data register for limits,activate the
CHK instruction exception.
DBcc Reg,Label check condition,decrement and branch
JMP Label jump to address(similar to BRA)
JSR Label jump to subroutine.Return address is
deposited on stack,RTS causes return to that
address.
NOP no operation
RESET reset peripherals(caution!)
RTE return from exception
RTR return with loading of flags
RTS return from subroutine(after BSR and JSR)
Scc <ea> set a byte to -1 when condition is met
STOP stop processing(caution!)
TRAP #n jump to an exception
TRAPV
Chapter 2, The MC68000 processor
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Assembler Coding